1. Field of the Invention
The present invention relates to an amplifier circuit configured to prevent breakdown of a transistor when an input signal is at a ground level.
2. Description of the Related Art
A related-art amplifier circuit is now described. FIG. 9 is a circuit diagram illustrating the related-art amplifier circuit.
The related-art amplifier circuit includes a constant voltage circuit 101 configured to output a constant voltage, NMOS transistors 103 and 104, a load 102, a ground terminal 100, an output terminal 106, and an input terminal 105.
The input terminal 105 inputs an input signal voltage Vin, and the output terminal 106 outputs an output signal voltage Vout. Because the amplitude of a drain voltage of the NMOS transistor 104 is small, the NMOS transistor 104 to be used may have a low breakdown voltage. Thus, the NMOS transistor 104 to be used may be a normal breakdown voltage MOS transistor having a large value of transconductance gm. On the other hand, the transconductance gm of the NMOS transistor 103 has almost no contribution to an amplification factor of the whole amplifier circuit. Thus, with use of a high breakdown voltage MOS transistor only for the NMOS transistor 103, the impedance of the load 102 can be set to be high so that large output voltage amplitude may be generated, to thereby increase the gain of the whole amplifier circuit (see, for example, FIG. 1 of Japanese Patent Application Laid-open No. 2005-311689).
However, the related-art amplifier circuit has a problem in that, when the input signal voltage Vin is at a ground level and the load 102 is capable of supplying a current, the drain of the NMOS transistor 104 becomes floating to generate a voltage equal to or higher than a breakdown voltage of the transistor, resulting in breakdown of the transistor.